Charge-coupled devices (CCDs) are used in conventional imaging circuits for converting the light incident on a pixel into an electrical signal that is proportional to the intensity of the incident light. In general, CCDs utilize a photogate to convert the incident photons into an electrical charge, and a series of electrodes to transfer the charge collected at the photogate to an output node.
Although CCDs have many strengths including a high sensitivity and fill-factor, CCDs also suffer from a number of weaknesses. Most notable among these weaknesses, which include limited readout rates and dynamic range limitations, is the difficulty in integrating CCDs with CMOS-based microprocessors.
To overcome the limitations of CCD-based imaging circuits, imaging circuits based on active pixel sensor cells have been developed. In an active pixel sensor cell, a conventional photodiode is combined with a number of active transistors which, in addition to forming an electrical signal representing the output of the photodiode, provide amplification, readout control, and reset control for the pixel. Arrays of active pixel sensor cells can be used in multimedia applications requiring low-cost and high functionality to acquire high quality images at video frame rates. Because the elements of an active pixel sensor are fabricated using a CMOS process flow, the sensor may easily be integrated into more complex CMOS-based devices to produce combined sensor-signal processor devices.
FIG. 1 is a schematic showing an example of a conventional CMOS active pixel sensor cell 10. As shown in the figure, cell 10 includes a photodiode 12 connected to a first intermediate node (labelled "node 1" in the figure), and a reset transistor 14 that has a drain connected to a power supply node N.sub.ps, a source connected to node 1, and a gate connected to a first input node (labelled "reset" in the figure).
Cell 10 further includes a buffer transistor 16 and a row-select transistor 18. Buffer transistor 16 has a drain connected to node N.sub.ps, a source connected to a second intermediate node (labelled "node 2" in the figure), and a gate connected to node 1. Row-select transistor 18 has a drain connected to node 2, a source connected to a third intermediate node (where the source line intersects the column data line in the figure), and a gate connected to a second input node (labelled "row select" in the figure).
The operation of cell 10 begins by briefly pulsing the gate of reset transistor 14 with a reset voltage V.sub.RESET at time t.sub.1. The reset voltage V.sub.RESET, which is equal to Vcc (typically, +5 V), resets the voltage on photodiode 12 to an initial integration voltage and begins an image collection cycle.
At this point, the initial integration voltage on photodiode 12 (as measured at node 1) is defined by the equation V.sub.RESET -V.sub.T14 -V.sub.CLOCK, where V.sub.T14 represents the threshold voltage of reset transistor 14, and V.sub.CLOCK represents reset noise from the pulsed reset voltage (assumed to be constant). Similarly, the initial integration voltage as measured at node 2 is defined by the equation V.sub.RESET -V.sub.TI4 -V.sub.CLOCK -V.sub.T16, where V.sub.T16 represents the threshold voltage of output buffer transistor 16 (functioning in a source follower mode).
After the reset voltage V.sub.RESET has been pulsed and the voltage on photodiode 12 (as measured at node 1) has been reset, a row-select voltage V.sub.RS is applied to the second input node (row select) at a time t.sub.2 which immediately follows the falling edge of the reset pulse V.sub.RESET. The row select voltage V.sub.RS causes the voltage on node 2, which represents the initial integration voltage of the cycle, to appear on the third intermediate node (where the source of row select transistor 18 intersects the column data line). Detection and calculation circuit 20 connected to the column data line then amplifies, digitizes, and stores the value of the initial integration voltage as it appears on the third intermediate node.
Detection and calculation circuit 20 typically contains a sense amplifier and a second amplifier which performs a correlated double sampling to compute the difference in the sense amplifier output prior to and after strobing charge out of the pixel. This acts to remove charge fluctuation on the column line (the kTC thermal charge noise component) during reset of the sense amplifier which might otherwise contribute to the readout signal. Circuit 20 is located off-pixel and is typically shared by all of the pixels in a column of an imaging array.
Next, from time t.sub.2, which represents the beginning of the image collection cycle, to a time t.sub.3, which represents the end of the image collection cycle, light energy, in the form of photons, strikes photodiode 12, thereby creating a number of electron-hole pairs. Photodiode 12 is designed to limit recombination between the newly formed electron-hole pairs. As a result, the photogenerated holes are attracted to the ground terminal of photodiode 12, while the photogenerated electrons are attracted to the positive terminal of photodiode 12. Each additional electron reduces the voltage on photodiode 12 (as measured at node 1). Thus, at the end of the image collection cycle, a final integration voltage will be present on photodiode 12.
At this point (time t.sub.3), the final integration voltage on photodiode 12 (as measured at node 1) is defined by the equation V.sub.RESET -V.sub.T14 -V.sub.CLOCK -V.sub.S, where V.sub.S represents the change in voltage due to the absorbed photons. Similarly, the final integration voltage as measured at node 2 is defined by the equation V.sub.RESET -V.sub.T14 -V.sub.CLOCK -V.sub.T16 -V.sub.S.
At the end of the image collection cycle (time t.sub.3), the row-select voltage V.sub.RS is again applied to the row select input node. The row select voltage V.sub.RS causes the voltage on the second intermediate node, which represents the final integration voltage of the cycle, to appear on the third intermediate node. Detection and calculation circuit 20 then amplifies and digitizes the value of the final integration voltage as it appears on the third intermediate node.
Following this, detection and calculation circuit 20 determines the number of photons that have been collected during the integration cycle by calculating the difference in voltage between the digitized final integration voltage taken at time t.sub.3 and the digitized stored initial integration voltage taken at time t.sub.2. At this point, the voltage difference is defined by the equation (V.sub.RESET -V.sub.T14 -V.sub.CLOCK V.sub.T16)-(V.sub.RESET -V.sub.T14 -V.sub.CLOCK -V.sub.T16 -V.sub.S), thereby yielding the value V.sub.S.
Once the final integration voltage has been digitized by the detection and calculation circuit, the reset voltage V.sub.RESET is again applied to the first input node at time t.sub.4, which immediately follows the rising edge of the row select voltage V.sub.RS at time t.sub.3. The reset voltage V.sub.RESET again resets the voltage on photodiode 12 to begin another image collection cycle.
Image processing of the pixel output is normally performed after the image is captured, converted to a digital format, and moved to a main memory where it is operated upon by the central processing unit. Each of these data manipulation or processing operations requires the consumption of power and acts to limit the maximum throughput rate for video signals. These factors are important for portable imaging applications, which represents a primary area of growth at the present time for active pixel sensors. Many of the basic image processing operations used in such applications require relatively simple arithmetic operations, e.g., the value of a pixel relative to its previous value or to that of adjacent pixels. Applications of such arithmetic operations include motion detection, image stabilization, and video compression.
For example, in order to perform video compression, the current output of a pixel (i.e., the pixel's photosensor) is read out of a pixel and then subtracted from the output corresponding to the previous frame, which had been read out and stored in an off-pixel storage element. A difference signal representing the change in the pixel output for successive frames is then sent to the periphery of the array. This subtraction operation is typically performed by a difference amplifier which is also located off-pixel. This approach requires less information to be transferred and processed external to the imaging cell than would be required to read out and store the two pixel values in main memory and have the processing unit perform the differencing operation. While this method reduces the power consumption and increases the system performance compared to storing both pixel values, it still requires significant off-pixel processing and system overhead. This is because it requires the system to read out one pixel output value, store it off-pixel, read out a second value and transfer it to a location off-pixel, and then perform the differencing operation.
The article entitled "TP 13.5: A 256.times.256 CMOS Active Pixel Image Sensor with Motion Detection", A. Dickinson et al., Digest of Technical Papers 1995 IEEE International Solid-State Circuits Conference, page 226 et seq., describes the use of an active pixel's floating diffusion output node as a dynamic storage element. The storage capability of the node is used to provide a signal representing the pixel output for a previous frame. This value is read out to the first of two sample and hold capacitors located off-pixel. The pixel output for the current frame is then read out to the second capacitor. The contents of the two capacitors are then provided as the inputs to a differential amplifier, with the amplifier output being a signal representing the difference between the pixel outputs for successive frames.
Although this structure can be used to generate the difference signal required for video compression, motion detection, etc., it has the disadvantage that the storage and control elements used to determine the difference between pixel outputs for successive frames are located off-pixel. The pixel itself generates only an output signal, either corresponding to the previous frame or the current frame. Because of this arrangement, each of the two signals needed to compute the difference of the pixel output for successive frames is read out separately and stored in its own off-pixel storage element. This increases the number of clock cycles required to process the pixel outputs to obtain the difference signal, thereby slowing down the operation of the imager.
What is desired is a structure for an active pixel image cell which includes an embedded memory element and the control elements needed to simultaneously generate as pixel outputs the signals required for determining the difference between the pixel output for successive frames. Generating the two outputs at the pixel level reduces the memory and processing demands of off-pixel processors, and increases the speed with which images can be acquired. It is also desired to have a structure for an active pixel image cell which includes elements for performing a differencing operation and generates an output signal representing the difference between pixel outputs for successive frames. These and other advantages of the present invention will be apparent to those skilled in the art upon a reading of the Detailed Description of the Invention together with the drawings.